The present exemplary embodiments pertain to the joining of electronic structures such as semiconductor devices to a laminate substrate and, in turn, the laminate substrate to other laminate substrates.
First, second and third level packages require the joining of multiple components onto the substrate. The first level package may be a chip scale package (CSP) to receive a semiconductor device, also referred to as a chip. The second level package may be a daughter card onto which one or more CSPs may be joined. The third level package may be a mother card (also known as a mother board) onto which one or more daughter cards may be joined.
There is a need to reduce the thermal exposure with each attachment of a component to a substrate and to avoid having the joints of the earlier joined components remelted to the point they move. If the earlier joined components move, the movement can lead to potential issues such as chip package interactions defects, solder extrusion, solder spitting, etc.
During the leaded period of microelectronics, it was possible to have joints made with high melt temperature leaded solder and low melt temperature leaded solder.
The introduction of lead free solders has brought a number of challenges with respect to the joining of multiple components on multiple levels of packages. The concept of having a high melt temperature solder joined to a low melt temperature solder was not pursued mainly due to a reduced delta in the melting point of the different lead free solders and their availability to have controlled plating on the chip side and availability of options on the substrate side.